Verilog and VHDL (VHSIC Hardware Description Language) are both hardware description language for hardware modeling.
In general, there are two conclusions:
- Verilog is used extensively for production level projects and in Industry
- VHDL is great for beginners who are yet to develop Hardware Design Principles
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This is a companion discussion topic for the original entry at http://iq.opengenus.org/verilog-vs-vhdl/